EEE 251 Logic Design and Circuits

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Gediz University, Computer Engineering Department
Fall Semester 2011
Tuesday: Lecture: 10:00 - 12:45, AZ02   Lab: 13:45 - 15:30

 
   Instructor: Halk Gmşkaya Teaching Assistant: Yavuz İnce
   Office: D107 Office: ....
   Office Hours: Mon, Wed, Thur: 13:00 - 13:45 Office Hours:
   Phone: 0232-355 0000 - 2305 Phone: 2321
   e-mail: haluk.gumuskaya@gediz.edu.tr e-mail:  yavuz.ince@gediz.edu.tr
   
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Course Description

  Laboratory:

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Prerequists

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Logic Design and Circuits Lab Home Page

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Lecture Schedule

bullet Weekly Schedule
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Grading

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Lab Policies

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Regulations

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Verilog Resources

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Textbooks

 
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Tools and Development Environments

 

  Course Description  (3-2-4)

Data representation, number systems, arithmetic operations, Boolean algebra, logic functions and theorems, logic gates, canonical forms, simplification techniques, design of combinational circuits, decoders, encoders, multiplexers, arithmetic circuits, sequential circuits, design of sequential circuits and the algorithmic state machine, timing and timing problems, programmable logic devices, registers and register operations, buses and 3-state logic, basics of memory, SRAM and DRAM, introduction to basic computer organization and design.

  Prerequisite

   None

  Lecture Schedule

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The syllabus (Course Inforamtion Form) given to students at the beginning of the semester.

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The lecture and lab schedules given in the syllabus are tentative and updated here weekly. Look at this table once a week.

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Almost all the slides used during the semester will be available via the following links or given to you.

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I may skip several slides during the lecture (The slides given would be generally too much!). They are included in the course material for completeness and to provide a good reference for your future professional engineering life.

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To follow the lecture and understand the materials presented in class better, get the lecture slides and take the print-outs of them, and please bring them to class.

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Purposes for bringing slides to class: 1) To allow better concentration in lecture by reducing note-taking pressure and to provide a study-aid before and after lecture.

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2) You can take your notes on these slides and be active during the lecture. You digest material much better when you actively take notes from step-to-step demonstrations given by your instructor than by just sitting and watching slides.

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Disclaimers: (a) I may not follow these slides exactly in class (b) I may also use the whiteboard and give some extra notes which will not be posted here as needed in class (c) Students are responsible for what I say and teach in class. (d) Reading these slides is not a substitute for attending lecture

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Lec

 Topics Covered

Lab

HW

1 27/09

Lec 1

Introduction: Digital and Binary Data Representation, DD Chp. 1

 

 

2 4/10

Lec 2

Combinational Logic Design: Switches, Transistors, Logic Gates, Boolean Algebra, DD Chp. 2.1-2.5

 

 

3 11/10

Lec 3
Lec 4

Truth Tables, Canonical Forms, Combinational Logic Design Process, Examples, DD Chp. 2.6-2.8   HW1
4 18/10

Lec 5
Lec 6

More Gates, Decoders and MUXes, Non-ideal Behavior, DD Chp. 2.9, 2.10 Lab1  
5 25/10

Lec 7

Combinational Logic Optimizations and Tradeoffs,  DD Chp. 6.1, 6.2 Lab2  
6 1/11

Lec 8

Sequential Logic Design: Controllers: Latches & Flip-Flops, Basic Register, Clocking,  DD Chp. 3.1-3.2 Lab3  
7 8/11 No classes, Kurban Bayram week
8 15/11   Midterm Exam I: 10:00 
Lab Tutorial: 13:00:
Introduction to Logic Design using BASYS 2 FPGA boards and Verilog
Lab  
9 22/11   FSMs, Controller design, examples, non-ideal behavior, Verilog modeling, DD Chp. 3.2, 3.4, 3.5, 3.8 Lab4  
10 29/11

Lec 9

Datapath Components: Registers, adders, Lab  
11 6/12   Comparator, multiplier, DD Chp. 4.1-4.5  Signed numbers, subtractors, ALUs, shifters, counters, timers, register file, Verilog modeling, DD Chp. 4.6-4.10, 4.13 Lab  
12 13/12

Lec 10

Register-Transfer Level (RTL) Design: High-level state machines HLSM, RTL design process, examples, DD Chp. 5.1-5.3 Lab5 HW2
13 20/12   Midterm Exam II: 10:00    
14 27/12   RTL design (continued), clock frequency, behavioral design, memory, RAM, ROM, DD DD Chp. 5.4-5.7 Lab6 HW3
15 3/01 Queues/FIFO, multiple processors, heirarchy, Verilog modeling, DD Chp. 5.6-5.10, 5.13

Lab7

10/01 Final Exam

  Textbooks

    Required

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Digital Design with RTL Design, Verilog and VHDL, 2nd ed., Frank Vahid, John Wiley, 2011.
All students are expected to obtain this textbook for use in labs, homework assignments, exams and class.

    Recommended

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Digital Design and Computer Architecture, D. Harris, S. Harris, Morgan Kaufmann, 2007.  

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Logic and Computer Design Fundamentals, 4th Ed., M. Morris Mano, C. Kime, Prentice Hall, 2008.

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Digital Design, 4th Ed., M. Morris Mano, M. D. Ciletti, Prentice Hall, 2007.

  Tools and Development Environments

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Hardware equipment provided in the Digital Systems Design Lab.

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A Digilent FPGA card (BASYS 2 or SPARTAN 3E STARTER).

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Design tools in the Xilinx environment.

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NI Circuit Design Suit 11.0 Multisim.

  Grading

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In order to pass EEE 251, students must show minimum competence in the exams. Any student who does not have a weighted average of 35.0 or greater for midterm and final exams will receive an automatic grade of FF, for lack of minimum competence.
The weighted average will be calculated as follows: (0.25 x Midterm Exams + 0.35 x Final Exam) / 0.60

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Attendance: Students who fail to attend at least 70% of the classes will receive a grade of FF.
Students must not miss more than 2 lab sessions (80% of the lab sessions), or they will receive a grade of FF.

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Students who meet the above requirements will have their numerical course average calculated with the following weights:
Labs:                    30%
Homework:          10%
Midterm Exam1:  10%
Midterm Exam2:  15%
Final Exam:          35%

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From the numerical course average grades, the students who meet the above two requirements, letter grades ranging from AA to FF will be determined in the usual way (taking into account overall performance and distribution of the scores, class and lab participation and effort, as well as the attendance (in class and lab) of the student.

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We will be very careful in grading the labs, homework assignments, exams so that everybody gets the grade that he/she deserves. Copying will not be tolerated and will be checked and punished rigorously.

 

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