COM 252 Computer Organization

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Gediz University, Computer Engineering Department
Spring Semester 2012
Monday, 13:45 - 16:30, DZ01

 
  Instructor: Halk Gmşkaya Teaching Assistant: Yavuz İnce
  Office: D107 Office: D216
  Office Hours: Mon, Tue, Wed: 13:00 - 13:45 Office Hours:
  Phone: 0232-355 0000 - 2305 Phone: 2334
  e-mail: haluk.gumuskaya@gediz.edu.tr e-mail: yavuz.ince@gediz.edu.tr
   
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Course Description

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Textbooks

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Prerequists

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Tools and Development Environments

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Lecture Schedule

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Processor Design Projects

 
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Grading

  Course Description   (3-0-3)

Basic computer organization and design. Instruction fetch, decode and execution cycles. Arithmetic and logic operations and design of arithmetic logic unit. CPU organization. Instruction formats and addressing modes. Hardwired and micro programmed control organization. Memory organization: static and dynamic memories and memory design, virtual-memory, caches and their management. Input-Output organization: interfacing processors and peripherals. Pipelining and other techniques for performance improvements. Machine language and assembly language.

  Course Objectives

Field Programmable Gate Arrays (FPGAs), containing the equivalent of thousands or millions of logic gates, make it possible to build complex digital systems in the lab or home without the tedium of manually connecting components. In this class, you will build your own microprocessor and test it on a FPGA. In the process, you will master the art and science of digital design. You will learn to speak to and control processors in their native tongue and use them to control the world. And you will put all the pieces together to demystify how a computer works.

Very few complex systems work the first time you put them together. Engineers must become good at systematically and efficiently debugging their designs. One of the course objectives that can be frustrating but vitally important is to learn to teach oneself professional-strength computer-aided design tools and to use these tools to debug systems.

We will use easy-to-follow books which blend traditional teaching approaches with the use of mathematics, together with the use of a hardware description language (Verilog) and a concrete processor (MIPS32) as vehicles for "hands-on" modeling and experimenting with digital logic and processor design.

By the end of this course, a successful student will be able to:
design and debug combinational and sequential digital circuits using schematics and Verilog
program in MIPS assembly language
build a microprocessor

  Prerequisite

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COM 252 Logic Design and Circuits.

  Lecture Schedule (tentative)

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D

Lec

Topics Covered

Lab

HW

1 13/02 Lec 1.1
Lec 1.2
Lec 1.3
Course Overview
Optimizations and Tradeoffs: Sequential Logic, Moore and Mealy Machines, Datapath Components, RTL Design
(chp. 6)
   
2 20/02

Lec 2

Physical Implementation on ICs (chp. 7)    
3 27/02

Lec 3

Programmable Processors (chp. 8)    
4 05/03

Lec 4

Sequential Logic Design: Moore and Mealy FSM Examples: Traffic Light Controller, Snail's Brain FSM, chp 3.3, 3.4    
5 12/03

 

Design (RTL design, controller and dataparth components, and FSM of controller) and Implementation of a Simple Processor having 3 instructions (Load, Store and Add) using Logisim Lab: Design of 3-Instruction CPU using Logisim  
6 19/03

Lec 5

Hardware Description Languages: Combinational Logic Description using HDLs, Sequential Logic Description using HDLs, Finite State Machines, Parameterized Modules, Testbenches, Datapath Component Description using HDLs, RTL Design using HDLs, (chp. 4.1-4.9 and chp 9 F.Vahid) Lab: Design of 3-Instruction CPU using Logisim (continued)  
7 26/03 Midterm Exam
8 02/04

Lec 6

Lec 7

Digital Building Blocks: Arithmetic Circuits, Fixed and Floating Point Number Systems, Sequential Building Blocks, Memory Arrays, Logic Arrays  (chp. 5)

Architecture: MIPS Instruction Set and Registers, Branches (chp. 6)

   
9 09/04  

Lec 8.1

Architecture: Procedure Calls, Addressing  (chp. 6)

Microarchitecture:
Single-Cycle MIPS Processor  (chp. 7)
Lab: Introduction to ModelSim (Traffic Lights Controller FSM)

Installation: Xilinx WebPACK, ModelSim, SPIM, and Spartan 3E Board
CAD Tool Hints

 
10 16/04 Lec 8.2 Microarchitecture: Multi-Cycle MIPS Processor Lab 1
Optional:
Lab 6, Lab 7
 
11 23/04   National Holiday, National Sovereignty and Children's Day in Turkey    
12 30/04 Lec 8.3 Microarchitecture: Pipelined MIPS Processor Lab 5 (ALU)
Lab 8 (Single-Cycle CPU)
 
13 07/05

Lec 9

Memory Systems: Memory System Performance Analysis, Caches (chp. 8) Lab 9 (Multi-Cycle CPU-Part 1)
Lab 10 (Multi-Cycle CPU-Part 2)
 
14 14/05   Memory Systems: Virtual Memory, Memory Mapped I/O, Course Summary Project Demonstrations  

  Textbooks

    Main Textbooks

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Digital Design and Computer Architecture, D. Harris, S. Harris, Morgan Kaufmann, 2007.

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Digital Design with RTL Design, Verilog and VHDL, 2nd ed., Frank Vahid, John Wiley, 2011.

    Recommended

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A Practical Introduction to Computer Architecture, D. Page, Springer, 2009. Support Page

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Computer Organization and Design: The Hardware/Software Interface, 4th Edition, John L. Hennessy & David A. Patterson, Morgan Kaufmann, 2011.

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Essentials of Computer Organization and Architecture, 3rd Edition, L. Null, J. Lobur, Jones and Bartlett Learning, 2010.

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Logic and Computer Design Fundamentals, 4th Ed., M. Morris Mano, C. Kime, Prentice Hall, 2008.

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Computer Organization & Architecture: Designing for Performance, 8th Ed., William Stallings, Prentice Hall, 2009.

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Computer Organization and Embedded Systems, C. Hamacher, Z. Vranesic, S. Zaky, N. Manjikian, 6th Edition, Mc Graw Hill, 2011.

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Structured Computer Organization, Andrew S. Tannenbaum, Prentice Hall, 1998.

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Computer System Architecture, 3rd Edition, M. Morris Mano, Prentice Hall, 1992.

  Tools and Development Environments

Students will design a microprocessor using design, simulation and implementation tools from the following tool set:

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Logisim  Logisim is an educational tool for designing and simulating digital logic circuits. It can be used to design and simulate entire CPUs for educational purposes. Look at YouTube Logisim Tutorials , 16-bit RISC Processor in Logism (with source files), Processor Design Project using Logisim at Berkeley, Spring 2012, Finite State Machines in Logisim

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ModelSim, HDL simulation and debugging for both VHDL and Verilog designs, ModelSim PE Student Edition

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SPIM: A MIPS32 Simulator

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Design tools in the Xilinx environment.

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A Digilent FPGA card (BASYS 2 or SPARTAN 3E STARTER).

   Processor Design Projects

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Verilog Implementation of the 10-Instruction Single-Cycle and Multi-Cycle 32-bit MIPS Processors (2 processor design projects)

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Verilog Implementation of the 10-Instruction Single-Cycle 32-bit MIPS Processor

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Logisim Implementation of the 10-Instruction Single-Cycle and Multi-Cycle 32-bit MIPS Processors (2 processor design projects)
 

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Verilog Implementation of the 6-Instruction 16-bit Processor (F. Vahid's Processor)

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Logisim Implementation of the 6-Instruction 16-bit Processor (F. Vahid's Processor)

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Verilog Implementation of the 3-Instruction 16-bit Processor (F. Vahid's Processor)
 

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Logisim Implementation of the 3-Instruction 16-bit Processor (F. Vahid's Processor) (Already done in the middle of the semester)

  Grading

    40
% : Labs
   
10 % : HW Assignments
    20 % : Midterm
    30
% : Final Exam

A Very Important Notice:

The only way to really master the material in this class is to design a processor. The labs in this class build upon each other until you design your own 32-bit MIPS processor in Labs 5, 8, 9, 10. You must complete these labs and demonstrate a working microprocessor to pass this class.
 

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